module Counter (
    input logic clk,
    input logic rst,
    input logic button,
    input logic en,
    output logic [4:0] ge,
    output logic [4:0] shi
);

logic button_prev; // 边沿检测寄存器
logic [7:0] value;

always_ff @(posedge clk or posedge rst) begin
    if (rst) begin
        value <= 0;
        button_prev <= 0;
    end else begin
        button_prev <= button; // 保存前一个状态
        if (en && !button_prev && button) begin // 检测上升沿
            value <= (value >= 99) ? 0 : value + 1; // 自动归零逻辑
        end
    end
end

always_comb begin
    ge = value % 10;
    shi = value /10 % 10; 
end

endmodule